Electronic devices and systems such as printers, copiers, electronic storage devices (memories) high definition television, enhanced definition television and computational devices (e.g. calculators and computers including personal computers, minicomputers, personal computers and microcomputers) requiring electronic storage devices, often provide data storage on an integrated circuit chip. Because these devices often require large amounts of storage space for many applications, these storage devices are embodied in memory, for instance, a dynamic random access memory (DRAM). Memory cells sometimes contain or are associated with defects. It is therefore necessary to replace defective memory or defect associated memory with memory from alternate memory cells commonly referred to as redundant memory. Once defective memory is detected, the address corresponding to this memory is noted and the mechanism for implementing the redundant memory cells is enabled before the memory is used. The mechanism for implementing the redundant memory cells is usually embodied in a system based on blowing fuses. The scheme for producing a signal indicative of the desire to use the redundant memory, or rather, to match the row address of the defective memory, is of extreme importance. This redundancy scheme forms an integral part of the dynamic random access memory. This scheme is also an integral part of the above described devices and systems, supplying substantial value to these and other devices and systems in which it is used.
FIG. 1a illustrates a schematic drawing of a prior art redundancy scheme. N-channel transistor 2 is connected to P-channel transistor 4 through fuse 14. The gates of transistors 4 and 2 are connected to a terminal for powering up the circuit as shown. The drain of transistor 4 is connected to the input of inverter 10 and the drain of P-channel transistor 6. The drain of P-channel transistor 6 is also connected to the gate of N-channel transistor 8. The output of inverter 10 is connected to the gate of N-channel transistor 12. The signals from an address bit and its complement, A.sub.N and A.sub.N-, respectively, are input into respective terminals of associated transistors 8 and 12. N represents integers from zero through N. A circuit such as the one illustrated in FIG. 1a exists for each set of address bits comprising an address bit and its complement. Each FIG. 1a circuit produces address factors R.sub.N from the input of address bits A.sub.N and A.sub.N-. In connection with using a redundant memory cell in place of a usual memory cell, fuse 14 is blown when address bit A.sub.N is at a logic high level. Consequently, a high level signal is input to the gate of transistor 8 and inverter 10, thus resulting in a turned on transistor 8 and a turned off transistor 12. Note that feed back through transistor 6 helps maintain this logic high level signal. Alternatively, if address bit A.sub.N is at a logic low level, fuse 14 is not blown. This results in a turned off transistor 8 and a turned on transistor 12.
FIG. 1b is a schematic drawing of the circuit which processes the address factors from a plurality of circuits of the type shown in FIG. 1a. Each address factor is input into the gate of a plurality of transistors each labeled 16. When an address match occurs such that memory is addressed needing replacement by redundant memory, the gates of transistors 16 connected to NAND gate 18 are each at a logic low level resulting in inputting a high logic level signal into NAND gate 18. Consequently, during a logic high enable signal to NAND gate 18, NAND gate 18 outputs a low level logic signal to inverter 20. Inverter 20 outputs a high logic level signal which enables the redundant memory cell word line for the current address. Note that the redundancy system implemented by FIG. 1b results in only replacing one memory cell word line at a time. Unfortunately, such single replacement system is inadequate given today's need for memory speed.
FIG. 1c illustrates a schematic drawing of a prior art redundancy scheme which allows multiple replacement of the usual memory cell word lines by redundant memory cell word lines. The circuit in FIG. 1c is similar to the circuit of FIG. 1b. Note that the most important difference lies in the fact that no address factor R.sub.0 (an address factor produced by address bits A.sub.0 and A.sub.0-) is used for input into a transistor 16. Consequently, this circuit results in replacing the use of two memory cell word lines with two redundant memory cell word lines during an address match since the least significant bit in an address makes no contribution by the way of address factors. During an address match with a logic high enable signal to NAND gate 18, NAND gate 18 outputs a logic low signal to inverter 20. NAND gate 18 and inverter 20 together implement an AND gate. Inverter 20 in turn outputs a high logic level signal. Depending on whether A.sub.0 or A.sub.0- is at a high logic level the output of inverter 22 or 24, each connected to the output of inverter 20, will transmit a low logic level to the input of inverters 26 or 28. This will result in either a high logic level signal on redundant word line RWL0 or RWL1. A high logic level signal on a redundant word line allows the use of redundant memory cells with gates connected to this word line. Note that the foregoing described multiple replacement system does not always allow multiple replacement of certain defective word lines such as is produced by certain word line to word line shorts. FIG. 2 is a diagram which illustrates this problem. Since address factor R.sub.0 is not used in the multiple replace scheme, addresses A.sub.0 and A.sub.1 can attain any state, logic zero or logic one, during an address match. Consequently, the regular word lines are replaced by the redundant memory lines two at a time during an address match such that all address bits past the last address bit are the same as the address one desires to match. Therefore, if A, B, C, and D represent word line to word line shorts between to adjacent word lines, it is easily seen that although shorts A and C can be corrected by the foregoing described multiple replacement scheme, shorts B and D cannot be replaced by the multiple replacement scheme. This problem is further illustrated by the chart below.
______________________________________ A2 A1 A0 ______________________________________ 0 0 0 0 0 1 0 1 0 0 1 1 ______________________________________
For a given address that requires a row address match for redundant memory use, addresses 000 and 001 are indistinguishable to the scheme. Such is also the case with addresses 010 and 011. Addresses 001 and 010 have different A.sub.1 bits. Therefore, it is impossible to simultaneously replace word lines corresponding to word line addresses 001 and 010 since no address bit match can occur at address bit A.sub.1. The prior art multiple replacement scheme solved this simultaneous replacement problem by blowing fuses so as to disregard not only address bit A.sub.0 but also address bit A.sub.1. This results in replacement of 4 word lines at a time rather than two word lines at a time. Extending this scheme further, in cases where address bit A.sub.2 presented a problem, the scheme replaced 8 word lines at a time. Unfortunately, as is apparent, such a solution does not always best allocate redundant word line resources. The following scheme presents a more efficient solution to the foregoing multiple replacement problem.